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The Bare (Board) Truth: I'm From CAM and I'm Here to Help
Wednesday, December 12, 2012 | Mark Thompson, CID, Prototron Circuits

Robert Burns once opined, “The best laid plans of mice and men often go awry.” And so it goes. Once again, this column will reiterate the basics about what designers need to do to control impedances.

I know that I’m beating this topic to death, but a recent experience dictates that I once again revisit the issue of controlled impedances and what is, or is not, called out on the drawing.

Not long ago, a longstanding customer had a design re-spin. It happened to be a high layer-count board that previously had controlled impedance. This particular story goes all the way back to the original design and prototyping of this product overseas.

The original design came in with a standard note about controlled impedances that said it all: The size of the traces being controlled, where they resided, and the threshold and tolerance they were to be, along with a proposed stack-up and standard allowance to be able to either resize traces or dielectrics to achieve the desired impedances. Fair enough. The job goes though the shop and ships along with Impedance test results.

A few weeks later, the customer needs a re-spin. This time no notes exist regarding any impedances, but amazingly, the precise stack-up we used last time was now put on the drawing. As you all know, this is not something I advise. A fabricator’s stack-up is the literal work stack-up being used. Not all fabricators incorporate a “nesting” value between layers, so a dielectric listed as, say .0074” may really press out to be .0068-.0069” depending on the layer interfaces.

By this, I mean:  Are they mainly copper as full planes? In that case, they may stay close to the .0074” in this example. Are they split planes? In that case, they may press slightly thinner to fill the porous areas around the metal on that layer.

Or are they pure signal layers? In that case, they may press out even thinner yet. For these reasons I do not recommend including a fabricator’s stack-up on the drawing. A fabricator’s stack-up that accounts for all the layer-nesting can often be worse if your fabricator is not careful and uses those figures as numbers prior to any pre preg nesting. But I digress...

Remember, the latest design is released without any notes regarding any controlled impedances, but now the drawing features the same stack-up used on a previous version. Then, a pure coincidence occurs in CAM during analysis of the latest design. Some gap violations on external layers that go below our current process minimums for the copper weight specified are due to a shift or offset in the surrounding copper pour. We contact the customer about the violations.

Did I mention that this part is an expedite?

Some hours go by before the customer responds with, “We see no such violations on our end. We have looked at both the design settings and the exported Gerbers and we suspect your software.” Additionally, the customer hesitated to change the outer layer starting copper weight to deal with the smaller gaps as it may affect the impedances.

OK, forget that we have been in business for years using this same CAM software package and have had no such issues at the analysis stage. The customer is always right. Indulge the customer. Another analysis is run with a completely different software package. Same results.


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