Join Xilinx and Mentor Graphics for a comprehensive analysis of multi-GHz SERDES links with HyperLynx and the Xilinx V5 AMI design kit. This analysis will enable designers to make the tradeoffs needed to attain cost-effective and robust SERDES channel designs.

This one-hour Webinar takes place January 28, 2010 at 2:00 p.m. EST.

During this Webinar, important aspects and key features of accurately analyzing multi-GHz SERDES links (such as PCIe 2.0) with IBIS AMI models in HyperLynx will be investigated. These include:

• The importance of an accurate time-domain characterization of the channel.
• HyperLynx's patent-pending adaptive worst-case bit sequence with AMI models and its impact on stressed eye density plots and bit error rate (BER) results.
• Fast channel simulation techniques with HyperLynx FastEye that allow you to quickly ensure optimal link performance within a range of conditions.
• The impact of the Power Distribution Network (PDN) on differential via behavior and BER performance.

The Webinar will also present a high-level overview of the Mentor design kit for Xilinx V5 high-speed I/O transceivers. The kit includes integrated support for IBIS AMI, as well as advanced tools for eye margin analysis and advanced results-viewing capabilities.

The presenters are Chuck Ferry of Mentor Graphics and Anthony Torza of Xilinx. Ferry is a Product Marketing Manager for high-speed tools at Mentor Graphics. Torza is a Technical Marketing Engineer for Xilinx specializing in SERDES products.

What You Will Learn

• The new IBIS 5.0 AMI modeling methodology for SERDES;
• How HyperLynx supports Xilinx IBIS-AMI Models;
• How to identify key features for accurate analysis of multi-GHz SERDES links with IBIS AMI models in HyperLynx; and
• The impact of the PDN on differential via behavior and BER performance.

Who Should Attend

• Systems designers who are adding high-speed serial links (e.g., PCIx, SATA-II) to their designs;
• Electrical engineers concerned with high-speed PCB design issues;
• Engineers facing SERDES design challenges;
• Anyone considering Xilinx Virtex-5;
• Signal integrity engineers; and
• HyperLynx customers interested in multi-GHz applications.

To register, click here.