Today's video equpment operates at gigabit rates, necessitating the use of large coaxial BNC connectors. Non-optimized BNC footrpints can cause impedance mismatches, reflections and signal loss. In this paper, Tsun-kit Chin of National Semiconductor discusses some common issues with BNC footprints, such as problems with the connector-to-board transition, and offers techniques for transparent footprint designs.

I've been busier than a one-armed paper-hanger lately, and I wanted to give you all an update: Great books, cool electronic projects and more Grammar 4 Engineers. Can you think of a better way to lead into Labor Day? I certainly can't! Then again, I am an engineer ... regardless, read on!

Designing differential pairs is challenging enough, and the "alphabet soup" of high-speed serial links such as SATA, SAS and XAUI create more problems as you move from 1 Gbps to 10 Gbps and beyond. Eric Bogatin discusses some of the cutting-edge design techniques he'll be teaching at his "Differential Pair Boot Camp" in Santa Clara on October 4.

What is "rheology" and why does "everything flow?" Chet Guiles examines the science of rheology and how understanding the rheology of the prepregs you use, during the time they melt and flow, can help a process engineer manage and control the lamination process.

Flexible circuit cables offer some significant advantages for facilitating the movement of data between elements of a system that must also be moved or flexed. However, there is a balancing act involved and there is more than one master to be served to create a system that is robust, reliable and easily manufacturable.

If a customer asks you to build a PCB that can withstand 20,000 volts, would you know how to build such a board? First things first: You cannot just say, "Well, I think FR-4 will work." It won't, and the board will fail. Boom! Here's how to avoid arc-overs, coronas and, most importantly, any booms.

Interconnect separation is usually expressed as a crack that propagates at the internal interconnection. This failure mode produces a crack that is wedge-shaped, with the large end on the side of the foil closest to the middle of the PWB. An interconnect failure frequently develops slowly over time, accumulating damage at a constant rate after onset.

In Part III of a series, we'll take a look at loop or mounted inductance. Loop inductance is important, for instance, when we need a reasonably accurate estimate for the Series Resonance Frequency (SRF), or for the anti-resonance peaking between two different-valued capacitors or between the capacitor's inductance and the static capacitance of the power/ground planes it connects to.

Traditionally, we've understood that a good, quiet power delivery system is one with lots of bypass capacitors. And it was easy to extend the understanding to the concept that more (bypass capacitors) is better. But there is another, better way to look at this whole issue. The concept of an "ideal" PDS impedance curve can be useful to keep in mind.

Nothing like a bit of Nietzsche to get one's brain going! In this edition of my series "Writing 4 Engineers" we look at the use of "that" and "which," which can get many of you in trouble. Or is it "that" can get many of you in trouble?