This application offers a system-level radar library to accelerate radar system development. System designers will welcome the full compatibility of their existing IP, while realizing more accurate real-world effects at an earlier architectural stage.

The deadline for the Technology Leadership Awards is September 24, 2010. The TLA recognizes engineers and CAD designers who use Mentor's innovative technology to address today's complex PCB systems design challenges and produce industry-leading products.

IPC has just released the B revision of IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard. IPC-7351B gives designers and board makers updated information on the diverse requirements of land pattern geometries for active and passive components designed for surface mounting.

The free evaluation version of CADSTAR 12.1 with all the latest functionality, is now available to download from Zuken.com. The Express version allows designers to see for themselves how easy it is to use CADSTAR and experience its powerful technology enabling capabilities.

This release offers new capabilities that increase productivity for RF system designers, including time delay neural network (TDNN) advanced amplifier behavioral models for capturing memory effects and measurement data interchange format (MDIF) model support.

E-System Design, Inc. is proud to be a Platinum sponsor of Eric Bogatin's Differential Signal Boot Camp event, taking place October 4, 2010 in Santa Clara, California.

Designing differential pairs is challenging enough, and the "alphabet soup" of high-speed serial links such as SATA, SAS and XAUI create more problems as you move from 1 Gbps to 10 Gbps and beyond. Eric Bogatin discusses some of the cutting-edge design techniques he'll be teaching at his "Differential Pair Boot Camp" in Santa Clara on October 4.

CST is hosting a series of technical Webinars focusing on the benefits that full-wave simulation brings to high-frequency/high-speed design. The events will focus on challenging applications and how advances in numerical techniques and computing technology have enabled fast turnaround and reduced prototyping costs.

Electronic Interconnect (EI) will exhibit at and participate in the upcoming Design-2-Part Show at the Von Braun Center in Huntsville, Alabama, September 14-15, 2010.

ANSYS has been ranked number 39 on the 2010 FORTUNE 100 Fastest-Growing Companies list. The ranking includes ANSYS as the sole provider of product development software, a recognition that underscores the strategic value of engineering simulation, as well as the ANSYS leadership position in this growing and critical market.

Today's video equpment operates at gigabit rates, necessitating the use of large coaxial BNC connectors. Non-optimized BNC footrpints can cause impedance mismatches, reflections and signal loss. In this paper, Tsun-kit Chin of National Semiconductor discusses some common issues with BNC footprints, such as problems with the connector-to-board transition, and offers techniques for transparent footprint designs.

Interconnect separation is usually expressed as a crack that propagates at the internal interconnection. This failure mode produces a crack that is wedge-shaped, with the large end on the side of the foil closest to the middle of the PWB. An interconnect failure frequently develops slowly over time, accumulating damage at a constant rate after onset.

Developers of mil/aero and other high-rel applications depend on solid failure analysis. Paul Reid discusses how thermal cycling will cause a robust plated through-hole to crack slowly over time. Plotting a resistance graph of damage accumulation allows technologists to determine onset, rate of accumulation and whether the damage is accelerating linearly or exponentially.

Andrew Goodwin, President of NorthBridge, said, "By working closely with OCM Manufacturing we can offer a true one-stop shopping experience for customers who wish to bring their ideas for electronics products to life without the overhead of hiring design engineers or bringing manufacturing assets in-house."

This paper examines the thermal properties of various halogen-free laminates used in handheld electronic products and correlates these properties with manufacturing requirements. Thermal properties investigated include z-axis CTE, time to delamination at 260°C and 288°C and temperature to decomposition.

Chairman Tony Abri, said, "Although we have a limited design capability, this new partnership will enable us to offer a much broader service--giving customers the satisfaction of knowing their products will be designed for manufacture, prototyped and, ultimately, built in production all managed through one channel."

Guest Editors Mark Thompson and Kelly Dack discuss techniques and materials for improving heat dissipation on PCBs, as well as the challenges designers face in trying to accurately calculate heat dissipation.

We all know the buzz words: impedance, 50 ohms, 10%, balanced lines, CTE, dielectric constant and loss and countless more. In this new series, PCB 101, I will break down some of these buzz words in layman's terms in the hopes that more people will understand what's happening inside the circuit.

Solder-free and 3-D assembly will help bridge the performance and density gaps needed to extend Moore's Law, as lithography on silicon runs out of steam. It will offer America the chance to restore her electronic manufacturing mojo and provide for her security. Please, America, don't miss this chance to leap-frog the rest of the world!

John Ritchie, Product Manager for Rogers Corporation, reviews his company's new high-frequency laminate product, RO4360, which features a Dk of 6.15. The new product can address issues concerning what Ritchie sees as three mega-trends in the industry: The drive toward mass transit, sustainable energy and Internet growth.

This Bleeding Edge is a bit different, though the word "bleeding" is quite appropriate. My ticker is on the mend and I'm feeling better. But I have to wonder: Did my 40 years of working with medical equipment companies save my life? I certainly believe so.

Today's video equpment operates at gigabit rates, necessitating the use of large coaxial BNC connectors. Non-optimized BNC footrpints can cause impedance mismatches, reflections and signal loss. In this paper, Tsun-kit Chin of National Semiconductor discusses some common issues with BNC footprints, such as problems with the connector-to-board transition, and offers techniques for transparent footprint designs.

Designing differential pairs is challenging enough, and the "alphabet soup" of high-speed serial links such as SATA, SAS and XAUI create more problems as you move from 1 Gbps to 10 Gbps and beyond. Eric Bogatin discusses some of the cutting-edge design techniques he'll be teaching at his "Differential Pair Boot Camp" in Santa Clara on October 4.

Interconnect separation is usually expressed as a crack that propagates at the internal interconnection. This failure mode produces a crack that is wedge-shaped, with the large end on the side of the foil closest to the middle of the PWB. An interconnect failure frequently develops slowly over time, accumulating damage at a constant rate after onset.

In Part III of a series, we'll take a look at loop or mounted inductance. Loop inductance is important, for instance, when we need a reasonably accurate estimate for the Series Resonance Frequency (SRF), or for the anti-resonance peaking between two different-valued capacitors or between the capacitor's inductance and the static capacitance of the power/ground planes it connects to.

Traditionally, we've understood that a good, quiet power delivery system is one with lots of bypass capacitors. And it was easy to extend the understanding to the concept that more (bypass capacitors) is better. But there is another, better way to look at this whole issue. The concept of an "ideal" PDS impedance curve can be useful to keep in mind.

Nothing like a bit of Nietzsche to get one's brain going! In this edition of my series "Writing 4 Engineers" we look at the use of "that" and "which," which can get many of you in trouble. Or is it "that" can get many of you in trouble?

Developers of mil/aero and other high-rel applications depend on solid failure analysis. Paul Reid discusses how thermal cycling will cause a robust plated through-hole to crack slowly over time. Plotting a resistance graph of damage accumulation allows technologists to determine onset, rate of accumulation and whether the damage is accelerating linearly or exponentially.

The characteristic impedance of a microstrip line is a complex function of frequency. Impedance changes are usually measured with time TDR, but does the observed impedance value depend upon rise time? What impedance value is actually visible in TDR of a line segment? Yuriy Shlepnev investigates in this app note.

Differential signaling is now the norm for carrying fast signals. Differential signal transmission, using tightly coupled parallel PCB tracks, is more reliable than the single-ended variety. John Berrie explains how to design multi-gig boards using built-in analysis tools.

This Bleeding Edge is a bit different, though the word "bleeding" is quite appropriate. My ticker is on the mend and I'm feeling better. But I have to wonder: Did my 40 years of working with medical equipment companies save my life? I certainly believe so.

Designing differential pairs is challenging enough, and the "alphabet soup" of high-speed serial links such as SATA, SAS and XAUI create more problems as you move from 1 Gbps to 10 Gbps and beyond. Eric Bogatin discusses some of the cutting-edge design techniques he'll be teaching at his "Differential Pair Boot Camp" in Santa Clara on October 4.

Interconnect separation is usually expressed as a crack that propagates at the internal interconnection. This failure mode produces a crack that is wedge-shaped, with the large end on the side of the foil closest to the middle of the PWB. An interconnect failure frequently develops slowly over time, accumulating damage at a constant rate after onset.

In Part III of a series, we'll take a look at loop or mounted inductance. Loop inductance is important, for instance, when we need a reasonably accurate estimate for the Series Resonance Frequency (SRF), or for the anti-resonance peaking between two different-valued capacitors or between the capacitor's inductance and the static capacitance of the power/ground planes it connects to.

Nothing like a bit of Nietzsche to get one's brain going! In this edition of my series "Writing 4 Engineers" we look at the use of "that" and "which," which can get many of you in trouble. Or is it "that" can get many of you in trouble?

Developers of mil/aero and other high-rel applications depend on solid failure analysis. Paul Reid discusses how thermal cycling will cause a robust plated through-hole to crack slowly over time. Plotting a resistance graph of damage accumulation allows technologists to determine onset, rate of accumulation and whether the damage is accelerating linearly or exponentially.

What? You don't know what "Nescio Quid Dicas" means? I'm shocked and horrified. I thought everyone knew that this is Latin for "I don't know what you're talking about." In "Writing 4 Engineers," you never know what you might learn!

To often, OEMs push PCB design projects onto their electrical engineers, computer technicians -- basically, anyone but the PCB designer. But it usually winds up costing the company time and money. That's what happens when companies try to trivialize our profession!

We all know the buzz words: impedance, 50 ohms, 10%, balanced lines, CTE, dielectric constant and loss and countless more. In this new series, PCB 101, I will break down some of these buzz words in layman's terms in the hopes that more people will understand what's happening inside the circuit.

If you're on software maintenance, you're really paying for your software vendor to be your team partner, 24/7/365. But if your support call gets lost in a black hole, you're left wondering, "What's the point of paying maintenance anyway?" Let me walk you through maintenance, from a product manager's point of view.